This invention relates in general to decoder circuits and in particular, to a decoder circuit having at least one detection stage implemented with a reduced capacitive loading on a precharge/discharge node in order to speed up the decoding time.
A typical application of decoder circuits is for address decoding. In one type of address decoder circuit, 2.sup.N address detection stages are required to decode n address bits. In this type of decoder circuit, each stage detects a different combination of the n address bits to which there are 2.sup.N possible combinations.
FIG. 1 illustrates an example of one address detection stage 10 of such an address decoder. This stage detects when five address bits, AD1 to AD5, are all HIGH, i.e., when the address is 11111. Detection of the 31 (2.sup.5 -1) other combinations of the five address bits AD1-AD5 are accomplished by forming 31 other address detection stages with 31 different combinations of inverters between the address bits AD1-AD5 and their respective transistors, T1 to T5, to which they are input.
For example, detection of the address 11110 can be accomplished by a second address detection stage that differs from that shown in FIG. 1 by having an inverter inserted between the address bit AD5 and the transistor T5; and detection of the address 11100 can be accomplished by a third address detection stage having inverters inserted between the address bit AD5 and the transistor T5, and the address bit AD4 and the transistor T4. Other inverter combinations to detect other address combinations can likewise be defined.
When a given address AD1-AD5 is input to all 32 stages simultaneously, only one address detection stage out of the 32 detects an address match by each of its transistors T1-T5 being turned ON, resulting in its output being HIGH. The outputs of the other address detection stages show no match by one or more its transistors T1-T5 being turned OFF, resulting in each of their outputs being LOW.
Each address detection stage includes two phases of operation: a precharge phase and a strobing phase. Referring back to FIG. 1, the precharge phase occurs when a STROBE signal is LOW, resulting in N-mos transistor M6 being turned OFF and P-mos transistor M5 being turned ON. Since P-mos transistor M5 is ON, node B and the input to an inverter INV2 are both raised to the voltage level of the voltage source VDD, and the output of the inverter INV2 and subsequently, the OUTPUT of the address detection stage 10, are both LOW. In addition, with the output of the inverter INV2 being LOW, the P-mos transistor M4 is also turned ON, which acts to also drive node B to the voltage level of the voltage source VDD.
Also connected to node B are a series of N-mos transistors, T1 to T5, as well as, the strobe controlled transistor M6 at the end of the series. With node B HIGH, N-mos transistor T1 turns ON if address bit AD1 is HIGH and is capable of conducting current through it. Likewise, N-mos transistor T2 turns ON if address bit AD2 is HIGH and is capable of conducting current through it if transistor T1 is ON; N-mos transistor T3 turns ON if address bit AD3 is HIGH and is capable of conducting current through it if both transistors T1 and T2 are ON; N-mos transistor T4 turns ON if address bit AD4 is HIGH and is capable of conducting current through it if transistors T1, T2 and T3 are all ON; and N-mos transistor T5 turns ON if address bit AD5 is HIGH and is capable of conducting current through it if transistors T1, T2, T3 and T4 are all ON.
Since the capability of conducting current through each succeeding transistor depends upon the turning on of all preceeding transistors, this type of stacking arrangement of transistors is commonly referred to as Domino type logic. Even with all the transistors T1-T5 turned on, however, current does not flow through the stack while transistor M6 remains turned OFF. Thus node B precharges to and remains charged to the voltage level of VDD since there is no current path to ground.
After charging node B up to the voltage level VDD, the STROBE signal is changed to HIGH. This initiates the strobing phase which acts to discharge node B if all the transistors T1-T5 are turned ON. With transistors T1-T5 turned ON, as well as, N-mos transistor M6 since its input, the STROBE signal, is HIGH, a discharge path from node B to ground VSS is available.
With node B being discharged to ground level, the input to inverter INV2 goes LOW and its output, as well as, the OUTPUT of the address detection stage 10, then goes HIGH. The HIGH state of the output of the address detection stage 10 then indicates that an address match has been found. Finally, with the output of the inverter INV2 being HIGH, P-mos transistor M4 turns OFF. With both P-mos transistors M4 and M5 turned OFF, node B no longer has access to the voltage source VDD, and consequently, discharges like a capacitor through the transistor stack.